Nonvolatile semiconductor memory device and method of writing into the same

ABSTRACT

In a method of writing into a nonvolatile semiconductor memory device including a resistance memory element which memorizes a high resistance state and a low resistance state and switches between the high resistance state and the low resistance state by an application of a voltage, a variable resistor is parallelly connected to the resistance memory element, and when the voltage is applied to the resistance memory element to switch the resistance memory element between the high resistance state and the low resistance state, a resistance value of the variable resistor is set corresponding to the resistance state of the resistance memory element so that a writing circuit for applying the voltage to the resistance memory element, and a synthetic resistor of the resistance memory element and the variable resistor make the impedance-matching.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of International Application No.PCT/JP2005/011243, with an international filing date of Jun. 20, 2005,which designating the United States of America, the entire contents ofwhich are incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a nonvolatile semiconductor memorydevice, more specifically, a nonvolatile semiconductor memory deviceusing a resistance memory element having a plurality of resistancestates of different resistance values and a method of writing into thesame.

Recently, as a new memory device, a nonvolatile semiconductor memorydevice called RRAM (Resistance Random Access Memory) is noted. The RRAMuses a resistance memory element which has a plurality of resistancestates of different resistance values, which are changed by electricstimulations applied from the outside and whose high resistance stateand low resistance state are corresponded to, e.g., information “0” and“1” to be used as a memory element. The RRAM highly potentially has highspeed, large capacities, low electric power consumption, etc. and isconsidered prospective.

The resistance memory element has a resistance memory material whoseresistance states are changed by the application of voltages sandwichedbetween a pair of electrodes. As the typical resistance memory material,oxide materials containing transition metals are known.

The nonvolatile semiconductor memory device using the resistance memoryelement is disclosed in, e.g., U.S. Pat. No. 6,473,332 (herein aftercalled Reference 1), Japanese published unexamined patent applicationNo. 2005-025914 (herein after called Reference 2), Japanese publishedunexamined patent application No. 2004-272975 (herein after calledReference 3), Japanese published unexamined patent application No.2004-110867 (herein after called Reference 4), A. Beck et al., Appl.Phys. Lett., Vol. 77, p. 139 (2000) (herein after called Reference 5),W. W. Zhuang et al., Tech. Digest IEDM 2002, p. 193 (herein after calledReference 6), and I. G. Baek et al., Tech. Digest IEDM 2004, p. 587(herein after called Reference 6).

However, in the resistance memory element using the resistance memorymaterial described above, the impedance of the cell much varies betweenthe resistance value in the high resistance state and the resistancevalue in the low resistance state, which makes the impedance matchingwith outside circuits difficult.

For example, TiO_(x), which is a typical transition metal oxide, has theresistance value at 0.5 V varied by about 3 places between the highresistance state and the low resistance state. Accordingly, when theimpedance in, e.g., the high resistance state is matched with that of anoutside circuit, the impedance matching with the outside circuit in thelow resistance state is largely broken, and reversely, when theimpedance is matched with the outside circuit in the low resistancestate, the impedance matching with the outside circuit in the highresistance state is largely broken. Consequently, in high speedoperations, voltage pulses are reflected at the connection with theoutside circuit, which makes it impossible to apply effectivelysufficient voltages to the resistance memory element both in the lowresistance state and the high resistance state.

When effectively sufficient voltages cannot be applied to the resistancememory element due to the impedance mismatching, the resistance statescannot be switched, which makes the writing and erasing impossible, anderrors take place. To prevent this, the pulse width is elongated to makethe voltage application time longer, but this lowers the operationspeed.

SUMMARY OF THE INVENTION

One possible object is to provide a nonvolatile semiconductor memorydevice using resistance memory elements memorizing a plurality ofresistance states of different resistance values, which can facilitatethe impedance matching between the memory cells and peripheral circuitsboth when the resistance memory elements are rewritten from the highresistance state to the low resistance state and when rewritten from thelow resistance state to the high resistance state, and the method ofwriting into the same.

According to one aspect of the present invention, there is provided amethod of writing into a nonvolatile semiconductor memory deviceincluding a resistance memory element which memorizes a high resistancestate and a low resistance state and switches between the highresistance state and the low resistance state by an application of avoltage, a variable resistor being parallelly connected to theresistance memory element, and when the voltage is applied to resistancememory element to switch the resistance memory element between the highresistance state and the low resistance state, a resistance value of thevariable resistor being set corresponding to a resistance state of theresistance memory element so that a writing circuit for applying thevoltage to the resistance memory element, and a synthetic resistor ofthe resistance memory element and the variable resistor make theimpedance-matching.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a graph showing the current-voltage characteristics of theresistance memory element using a bipolar resistance memory material.

FIGS. 2 and 3 are graphs showing the current-voltage characteristics ofthe resistance memory element using a unipolar resistance memorymaterial.

FIG. 4 is a graph showing the current-voltage characteristics of theresistance memory element using a unipolar resistance memory material,which explains the forming process thereof.

FIGS. 5 and 6 are circuit diagrams showing the structure of thenonvolatile semiconductor memory device according to a first embodimentof the present invention.

FIGS. 7 and 8 are time charts showing the method of writing into thenonvolatile semiconductor memory device according to the firstembodiment of the present invention.

FIG. 9 is a time chart showing the method of reading the nonvolatilesemiconductor memory device according to the first embodiment of thepresent invention.

FIGS. 10 and 11 are circuit diagrams showing the structure of thenonvolatile semiconductor memory device according to a third embodimentof the present invention.

FIG. 12 is a circuit diagram showing the structure of the nonvolatilesemiconductor memory device and the method of writing into the sameaccording to a fifth embodiment of the present invention.

FIG. 13 is a plan view showing the structure of the nonvolatilesemiconductor memory device according to a sixth embodiment of thepresent invention.

FIG. 14 is a diagrammatic sectional view showing the structure of thenonvolatile semiconductor memory device according to the sixthembodiment of the present invention.

FIGS. 15A-15E are sectional views showing the method of manufacturingthe nonvolatile semiconductor memory device according to the sixthembodiment of the present invention.

FIG. 16 is a circuit diagram showing the structure of the nonvolatilesemiconductor memory device according to a modification of theembodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION A First Embodiment

The nonvolatile semiconductor memory device and method of writing intothe same according to a first embodiment of the present invention willbe explained with reference to FIGS. 1 to 9.

FIG. 1 is a graph showing the current-voltage characteristics of theresistance memory element using a bipolar resistance memory material.FIGS. 2 and 3 are graphs showing the current-voltage characteristics ofthe resistance memory element using a unipolar resistance memorymaterial. FIG. 4 is a graph showing the current-voltage characteristicsof the resistance memory element using a unipolar resistance memorymaterial, which explains the forming process thereof. FIGS. 5 and 6 arecircuit diagrams showing the structure of the nonvolatile semiconductormemory device according to the present embodiment. FIGS. 7 and 8 aretime charts showing the method of writing into the nonvolatilesemiconductor memory device according to the present embodiment. FIG. 9is a time chart showing the method of reading the nonvolatilesemiconductor memory device according to the present embodiment.

First, the basic operation of the resistance memory element will beexplained with reference to FIGS. 1 and 2.

The resistance memory element includes the resistance memory materialsandwiched between a pair of electrodes. Many of the resistance memorymaterial are oxide materials containing transition metals, and theresistance memory material is divided largely in two, depending ondifferences in the electric characteristics.

One of them uses voltages of different polarities so as to change theresistance states between the high resistance state and the lowresistance state and includes SrTiO₃ and SrZrO₃ doped with a trace of animpurity, such as chrome (Cr) or others, and Pr_(1-x)Ca_(x)MnO₃ andLa_(1-x)Ca_(x)MnO₃, etc., which exhibit CMR (ColossalMagneto-Resistance). Such resistance memory material which requiresvoltages of different polarities so as to rewrite the resistance statewill be hereinafter called the bipolar resistance memory material.

The other of them is materials which require voltages of the samepolarity so as to change the resistance states between the highresistance state and the low resistance state and includes oxides, etc.,containing a single transition metal, such as NiO_(x) and TiO_(x). Suchresistance memory materials which require voltages of the same polarityfor rewriting the resistance states will be hereinafter called theunipolar resistance memory material.

FIG. 1 is a graph of the current-voltage characteristics of theresistance memory element using the bipolar resistance memory materialand is disclosed in Reference 2. This graph is of the resistance memoryelement using Cr-doped SrZrO₃, which is the typical bipolar resistancememory material.

It is assumed that in the initial state, the resistance memory elementis in the high resistance state.

As an applied voltage increases gradually from 0 V to negative voltages,the current flowing at this time changes along the curve “a” in thearrowed direction, and its absolute value gradually increases. When theapplied negative voltage is further increased and exceed about −0.5 V,the resistance memory element switches from the high resistance state tothe low resistance state. Accompanying this, the absolute value of thecurrent abruptly increases, and the current-voltage characteristicstransits from the point A to the point B. In the following explanation,the operation of changing the resistance memory element from the highresistance state to the low resistance state is called “set”.

As the negative voltage is gradually decreased from the state at thepoint B, the current changes along the curve “b” in the arroweddirection, and its absolute value gradually decreases. When the appliedvoltage returns to 0 V, the current also becomes 0 A.

As the applied voltage increases gradually from 0 V to positivevoltages, the current value changes along the curve “c” in the arroweddirection, and its absolute values gradually increases. The appliedpositive voltage further increases and exceeds about 0.5 V, theresistance memory element switches from the low resistance state to thehigh resistance state. Accompanying this, the absolute value of thecurrent abruptly decreases, and the current-voltage characteristicstransit from the point C to the point D. In the following explanation,the operation of changing the resistance memory element from the lowresistance state to the high resistance state is called “reset”.

As the positive voltage decreases from the state at the point D, thecurrent changes along the curve “d” in the arrowed direction, and itsabsolute value gradually decreases. When the applied voltage returns to0 V, the current also becomes 0 A.

The respective resistance states are stable in the range of about ±0.5 Vand can be retained even when the electric power source is turned off.That is, in the high resistance state, when an applied voltage is lowerthan the absolute value of the voltage at the point A, thecurrent-voltage characteristics changes linearly along the curves “a”and “d”, and the high resistance state is retained. Similarly, in thelow resistance state, when an applied voltage is lower than the absolutevalue of the voltage at the point C, the current-voltage characteristicschanges linearly along the curves “b” and “c”, and the low resistancestate is retained.

As described above, for the resistance memory element using the bipolarresistance memory material, to change the resistance state between thehigh resistance state and the low resistance state, voltages ofdifferent polarities are applied.

FIG. 2 is a graph of the current-voltage characteristics of theresistance memory element using the unipolar resistance memory material.This graph is of the resistance memory element using TiO_(x), which isthe typical unipolar resistance memory material.

It is assumed that in the initial state, the resistance memory elementis in the high resistance state.

As an applied voltage is increased gradually from 0 V, the currentincreases along the curve “a” in the arrowed direction, and its absolutevalue gradually increases. When the applied voltage gradually increasesand exceeds about 1.3 V, the resistance memory element is switched fromthe high resistance state to the low resistance state (set).Accompanying this, the absolute value of the current abruptly increases,and the current-voltage characteristics transit from the point A to thepoint B. In FIG. 2, the current value at the point B is constantly about20 mA because of the current limiter for preventing the element frombreaking due to abrupt current increases.

As the voltage decreases gradually from the state at the point B, thecurrent changes along the curve “b” in the arrowed direction, and itsabsolute value gradually decreases. When the applied voltage returns to0 V, the current also becomes 0 A.

As the applied voltage again increases gradually from 0 V, the currentchanges along the curve “c” in the arrowed direction, and its absolutevalue gradually increases. When the applied positive voltage furtherincreases and exceeds about 1.2 V, the resistance memory element isswitched from the low resistance state to the high resistance state(reset). Accompanying this, the absolute value of the current abruptlydecreases, and the current-voltage characteristics transits from thepoint C to the point D.

As the voltage is decreased gradually from the point D, the currentchanges in the arrowed direction along the curve “d”, and the absolutevalue is gradually decreased. When the applied voltage returns to 0 V,the current also becomes 0 A.

The respective resistance states are stable not more than about 1.0 Vand are retained when the electric power is turned off. That is, in thehigh resistance state, when the applied voltage is below the voltage atthe point A, the current-voltage characteristics linearly change alongthe curve “a”, and the high resistance state is retained. Similarly, inthe low resistance state, when the applied voltage is below the voltageat the point C, the current-voltage characteristics change along thecurve “c”, and the low resistance state is retained.

As described above, in the resistance memory element using the unipolarresistance memory material, to change the resistance state between thehigh resistance state and the low resistance state, voltages of the samepolarity are applied.

FIG. 3 logarithmically expresses the current axis of the current-voltagecharacteristics of FIG. 2. As shown, TiO_(x), which is the typicalunipolar resistance memory material, the resistance values at 0.5 V aredifferent by about 3 places between the high resistance state and thelow resistance state. Accordingly, for example, when the impedance inthe high resistance state is matched with an outside circuit, theimpedance matching with the outside circuit in the low resistance statelargely breaks, and reversely, when the impedance in the low resistancestate is matched with the outside circuit, the impedance matching withthe outside circuit largely breaks for the high resistance state.

The resistance memory element formed of the above-described materialcannot have the characteristics shown in FIGS. 1 and 2 in the initialstate immediately after the element formation. To make the resistancememory material reversibly changeable between the high resistance stateand the low resistance state, the processing called “forming” isnecessary.

FIG. 4 shows the current-voltage characteristics explaining the formingprocess of the resistance memory element using the same unipolarresistance memory material as in FIGS. 2 and 3.

In the initial state immediately after the element has been formed, asshown in FIG. 4, the element is highly resistive and has a breakdownvoltage of about 8 V which is very high. This breakdown voltage is veryhigh in comparison with voltages necessary for the setting andresetting. In the initial state, changes of the resistance state, suchas the setting and resetting, do not take place.

When a voltage higher than the breakdown voltage is applied in theinitial state, as shown in FIG. 4, the value of the current flowingthrough the element abruptly increases, that is, the forming of theresistance memory element is made. Such forming is made, whereby theresistance memory element exhibits the current-voltage characteristicsshown in FIG. 2 and can switch reversibly between the low resistancestate and the high resistance state. Once subjected to the forming, theresistance memory element does not return to the initial state.

The resistance memory element in the initial state before subjected tothe forming has a high resistance value, and this high resistance statemight be misunderstood to be the high resistance state after theforming. Then, in the specification of the present application, the highresistance state means the high resistance state of the resistancememory element after subjected to the forming, the low resistance statemeans the low resistance state of the resistance memory element aftersubjected to the forming, and the initial state is the state of theresistance memory element before subjected to the forming.

The above-explanation has been made for the unipolar resistance memorymaterial, but the explanation is the same with the bipolar resistancememory material.

Next, the structure of the nonvolatile semiconductor memory deviceaccording to the present embodiment will be explained with reference toFIGS. 5 and 6.

FIGS. 5 and 6 are circuit diagrams showing the structure of thenonvolatile semiconductor memory device according to the presentembodiment.

As shown in FIG. 5, a memory cell 10 of the nonvolatile semiconductormemory device according to the present embodiment includes a resistancememory element 12 and a cell select transistor 14. The resistance memoryelement 12 has one end connected to a source line SL and the other endconnected to the source terminal of the cell select transistor 14. Thecell select transistor 14 has the drain terminal connected to a bit lineBL and the gate terminal connected to a word line WL.

The resistance memory element 12 includes a resistance memory materialsandwiched between a pair of electrodes. The resistance memory materialmay be a bipolar resistance memory material or a unipolar resistancememory material. In the present embodiment, the resistance memorymaterial is a unipolar resistance material of, e.g. TiO_(x).

Between the bit line BL and the source line SL, an impedance controltransistor 16 is connected in parallel with the memory cell 10.

FIG. 6 is a circuit diagram of a memory cell array of the memory cells10 shown in FIG. 5 arranged in a matrix. A plurality of memory cells 10are formed adjacent to each other in the column direction (vertically inthe drawing) and in the row direction (horizontally in the drawing).

In the column direction, a plurality of word lines WL1, WL2 . . . arearranged, forming signal lines common among the memory cells 10 arrangedin the column direction.

In the row direction (horizontally in the drawing), a plurality of bitlines BL1, BL2, BL3, BL4 . . . are arranged, forming signal lines commonamong the memory cells 10 arranged in the row direction.

In the column direction, source lines SL1, SL2 . . . are also arranged,forming signal lines common among the memory cells 10 arranged in thecolumn direction. The source lines SL are provided each for two bitlines BL.

Between each source line SL and two bit lines BL associated with thesource line SL, the impedance control transistor 16 is provided. Thus,the impedance control transistor 16 is common among a plurality of thememory cells 10 arranged in the row direction.

Next, the method of writing into the nonvolatile semiconductor memorydevice according to the present embodiment shown in FIG. 6 will beexplained with reference to FIGS. 7 and 8.

First, the rewriting operation from the high resistance state to the lowresistance state, i.e., the setting operation will be explained withreference to FIG. 7. A memory cell 10 to be rewritten is a memory cell10 connected to the word line WL1 and the bit line BL1.

First, a prescribed voltage is applied to the gate terminal of theimpedance control transistor 16 to turn on the impedance controltransistor 16 (see FIG. 7). At this time, the channel resistance R_(IC)of the impedance control transistor 16 is controlled by the voltageapplied to the gate terminal to thereby make an impedance as seen fromthe outside of the memory cell, i.e., an impedance between the bit lineBL and the source line SL not more than a resistance value R_(L) of theresistance memory element 12 in the low resistance state. The impedanceas seen from the outside of the memory cell can be set not more than theresistance value R_(L) of the resistance memory element 12 in the lowresistance state by setting the channel resistance R_(IC) of theimpedance control transistor 16 not more than the resistance value R_(L)of the resistance memory element 12 in the low resistance state.

To approximate the impedance of the memory cell with the resistancememory element 12 in the low resistance state to the impedance of thememory cell with the resistance memory element 12 in the high resistancestate, it is preferable to control the channel resistance R_(IC) of theimpedance control transistor 16 to be much smaller than the resistancevalue R_(L) of the resistance memory element 12 in the low resistancestate, preferably not more than ½, more preferably not more than ⅕,further more preferably not more than 1/10.

Concurrently with turning on the impedance control transistor 16, aprescribed voltage is applied to the word line WL₁ to turn on the cellselect transistor 14 (see FIG. 7). At this time, the voltage to beapplied to the word line WL₁ is controlled so that the channelresistance R_(CS) of the cell select transistor 14 is ignorably small incomparison with the resistance value R_(L) of the resistance memoryelement 12 in the low resistance state.

The source line SL1 is connected to a reference potential, e.g., 0 V,which is the ground potential (see FIG. 7).

The applied voltages to the impedance control transistor 16 and to thecell select transistor 14 are thus set, whereby the channel resistanceR_(IC) of the impedance control transistor 16 is ignorably small incomparison with the resistance value R_(H) of the resistance memoryelement, and the impedance between the bit line BL1 and the source lineSL1 is

R _(H) ×R _(IC)/(R _(H) +R _(IC))≈R _(IC).

Then, a bias voltage which is equal to or a little higher than thevoltage necessary to set the resistance memory element 12 is applied tothe bit line BL1 (see FIG. 7). Thus, a current path to the source lineSL1 via the bit line BL1, the resistance memory element 12 and the cellselect transistor 14 is formed, and the applied bias voltage is dividedto the resistance memory element 12 and the cell select transistor 14,corresponding to the resistance value R_(H) of the resistance memoryelement 12 and the channel resistance R_(CS) of the cell selecttransistor 14.

At this time, because of the resistance value R_(H) Of the resistancememory element 12, which is sufficiently large in comparison with thechannel resistance R_(CS) of the cell select transistor, most of thebias voltage is applied to the resistance memory element 12. Thus, theresistance memory element 12 is changed from the high resistance stateto the low resistance state.

Then, the bias voltage to be applied to the bit line BL1 is returned tozero, and then the voltage to be applied to the gate terminal of theimpedance control transistor 16 and the voltage to be applied to theword line WL1 are turned off. Thus, the setting operation is completed(see FIG. 7).

Next, the rewriting operation from the low resistance state to the highresistance state, i.e., the resetting operation will be explained withreference to FIG. 8. The memory cell 10 to be rewritten is a memory cell10 connected to the word line WL1 and the bit line BL1.

First, a prescribed voltage is applied to the gate terminal of theimpedance control transistor 16 to turn on the impedance controltransistor 16 (see FIG. 8). At this time, the channel resistance R_(IC)of the impedance control transistor 16 is controlled by the voltageapplied to the gate terminal to thereby make an impedance as seen fromthe outside of the memory cell, i.e., an impedance between the bit lineBL and the source line SL not more than a resistance value R_(L) of theresistance memory element 12 in the low resistance state. The impedanceas seen from the outside of the memory cell can be set not more than theresistance value R_(L) of the resistance memory element 12 in the lowresistance state by setting the channel resistance R_(IC) of theimpedance control transistor 16 not more than the resistance value R_(L)of the resistance memory element 12 in the low resistance state.

To approximate the impedance of the memory cell with the resistancememory element 12 in the low resistance state to the impedance of thememory cell with the resistance memory element 12 in the high resistancestate, it is preferable to control the channel resistance R_(IC) of theimpedance control transistor 16 to be much smaller than the resistancevalue R_(L) of the resistance memory element 12 in the low resistancestate, preferably not more than ½, more preferably not more than ⅕,further more preferably not more than 1/10.

Concurrently with turning on the impedance control transistor 16, aprescribed voltage is applied to the word line WL₁ to turn on the cellselect transistor 14 (see FIG. 8). At this time, the voltage to beapplied to the word line WL1 is controlled so that the channelresistance R_(CS) of the cell select transistor 14 is ignorably small incomparison with the resistance value R_(L) of the resistance memoryelement 12 in the low resistance state.

The source line SL1 is connected to a reference potential, e.g., 0 V,which is the ground potential (see FIG. 8).

The applied voltages to the impedance control transistor 16 and to thecell select transistor 14 are thus set, whereby the channel resistanceR_(IC) of the impedance control transistor 16 is ignorably small incomparison with the resistance value R_(L) of the resistance memoryelement, and the impedance between the bit line BL1 and the source lineSL1 is

R _(L) ×R _(IC)/(R _(L) +R _(IC))≈R _(IC).

That is, this impedance value is substantially equal to the impedancebetween the bit line BL1 and the source line SL1 when set.

Then, a bias voltage which is equal to or a little higher than thevoltage necessary to reset the resistance memory element 12 is appliedto the bit line BL1 (see FIG. 8). Thus, a current path to the sourceline SL1 via the bit line BL1, the resistance memory element 12 and thecell select transistor 14 is formed, and the applied bias voltage isdivided to the resistance memory element 12 and the cell selecttransistor 14, corresponding to the resistance value R_(L) of theresistance memory element 12 and the channel resistance R_(CS) of thecell select transistor 14.

At this time, because of the channel resistance R_(CS) of the cellselect transistor 14 which is sufficiently smaller than the resistancevalue R_(L) of the resistance memory element 12, most of the appliedbias voltage is applied to the resistance memory element 12. Thus, theresistance memory element 12 is changed from the low resistance state tothe high resistance state.

As described above, in the resetting processing, instantaneously withresetting the resistance memory element 12 to the high resistance state,substantially all the bias voltage is divided to the resistance memoryelement 12, and it is necessary to prevent the resistance memory element12 from being again reset by this bias voltage. Accordingly, the biasvoltage to be applied to the bit line BL is set to be less than avoltage necessary for setting.

That is, in the resetting process, the channel resistance R_(CS) of thecell select transistor 14 is adjusted to be sufficiently smaller thanthe resistance value R_(L) of the resistance memory element, and thebias voltage to be applied to the bit line BL is set to be not less thana voltage necessary for resetting and less than a voltage necessary forsetting.

Then, the bias voltage to be applied to the bit line BL1 is returned tozero. Then, the voltage to be applied to the gate terminal of theimpedance control transistor 16 and the voltage to be applied to theword line WL are turned off. Thus the resetting operation is completed(see FIG. 8).

In the nonvolatile semiconductor memory device according to the presentembodiment, in the resetting operation described above, by concurrentlydriving a plurality of bit lines BL (e.g., BL1-BL4), a plurality memorycells 10 connected to the selected word line (e.g., WL1) can be reset atonce.

Next, the method of reading the nonvolatile semiconductor memory deviceaccording to the present embodiment shown in FIG. 6 will be explainedwith reference to FIG. 9. A memory cell 10 to be read is the memory cell10 connected to the word line WL1 and the bit line BL1.

First, a prescribed voltage is applied to the word line WL1 to turn onthe cell select transistor 14 (see FIG. 9). At this time, the voltage tobe applied to the word line WL1 is controlled so that a channelresistance R_(CS) of the cell select transistor 14 is sufficientlysmaller than a resistance value R_(L) of the resistance memory element12 in the low resistance state.

In the reading operation of the nonvolatile semiconductor memory deviceaccording to the present embodiment, the impedance control transistors16 are not used. That is, the impedance control transistors 16 areturned off (see FIG. 9).

The source line SL1 is connected to a reference voltage, e.g., 0 V,which is the ground potential (see FIG. 9).

Then, to the bit line BL1, a prescribed bias voltage which does notcause the setting and the resetting is applied (see FIG. 9). When theresistance memory element 12 has the current-voltage characteristics of,e.g., FIG. 2, the bias voltage is set so that a voltage of not more thanabout 1.0 V is applied to the resistance memory element 12.

When such bias voltage is applied to the bit line BL, a currentcorresponding to the resistance value of the resistance memory element12 flows in the bit line BL1. A value of the current flowing in the bitline BL1 is detected, whereby a resistance state of the resistancememory element 12 can be read.

As described above, according to the present embodiment, the impedancecontrol transistor is provided, parallelly connected to the resistancememory element, and in a rewriting, the resistance value of theimpedance control transistor is set sufficiently smaller than theresistance value of the resistance memory elements in the low resistancestate, whereby the impedance as seen from the outside of the memory cellcan be made substantially equal in a rewriting, irrespective ofresistance states of the resistance memory elements. Thus, both when thememory cell is rewritten from the high resistance state to the lowresistance state and when the memory cell is rewritten from the lowresistance state to the high resistance state, the impedance matchingbetween the peripheral circuit and the memory cell can be easily made.

A Second Embodiment

The nonvolatile semiconductor memory device, the method of writing intothe same and the method of reading the same according to a secondembodiment of the present invention will be explained. The same membersof the present embodiment as those of the nonvolatile semiconductormemory device, the method of writing into the same and the method ofreading the same according to the first embodiment shown in FIGS. 1 to 9are represented by the same reference numbers not to repeat or tosimplify their explanation.

The nonvolatile semiconductor memory device according to the presentembodiment is the same as the nonvolatile semiconductor memory deviceaccording to the first embodiment shown in FIGS. 5 and 6 except that inthe former, the resistance memory element 12 is formed of the bipolarresistance memory material. The bipolar resistance memory material canbe, e.g., SrZrO₃ doped with Cr or others. To the resistance memoryelement of the nonvolatile semiconductor memory device according to thepresent embodiment, as shown in, e.g., FIG. 1, a negative bias voltageis applied in the setting, and, in the resetting, a positive biasvoltage is applied.

Then, the method of writing into the nonvolatile semiconductor memorydevice according to the present embodiment will be explained. The methodof writing into the nonvolatile semiconductor memory device according tothe present embodiment is basically the same as the method of writinginto the nonvolatile semiconductor memory device according to the firstembodiment except that the polarity of the bias voltage.

First, the rewriting operation from the high resistance state to the lowresistance state, i.e., the setting operation will be explained. Amemory cell 10 to be rewritten is a memory cell 10 connected to the wordline WL1 and the bit line BL1.

First, a prescribed voltage is applied to the gate terminal of theimpedance control transistor 16 to turn on the impedance controltransistor 16. At this time, the channel resistance R_(IC) of theimpedance control transistor 16 is controlled by the voltage applied tothe gate terminal to thereby make an impedance as seen from the outsideof the memory cell, i.e., an impedance between the bit line BL and thesource line SL not more than a resistance value R_(L) of the resistancememory element 12 in the low resistance state. The impedance as seenfrom the outside of the memory cell can be set not more than theresistance value R_(L) of the resistance memory element 12 in the lowresistance state by setting the channel resistance R_(IC) of theimpedance control transistor 16 not more than the resistance value R_(L)of the resistance memory element 12 in the low resistance state.

To approximate the impedance of the memory cell with the resistancememory element 12 in the low resistance state to the impedance of thememory cell with the resistance memory element 12 in the high resistancestate, it is preferable to control the channel resistance R_(IC) of theimpedance control transistor 16 to be much smaller than the resistancevalue R_(L) of the resistance memory element 12 in the low resistancestate, preferably not more than ½, more preferably not more than ⅕,further more preferably not more than 1/10.

Concurrently with turning on the impedance control transistor 16, aprescribed voltage is applied to the word line WL1 to turn on the cellselect transistor 14. At this time, the voltage to be applied to theword line WL1 is controlled so that the channel resistance R_(CS) of thecell select transistor 14 is ignorably small in comparison with theresistance value R_(L) of the resistance memory element 12 in the lowresistance state.

The source line SL1 is connected to a reference potential, e.g., 0 V,which is the ground potential.

The applied voltages to the impedance control transistor 16 and to thecell select transistor 14 are thus set, whereby the channel resistanceR_(IC) of the impedance control transistor 16 is ignorably small incomparison with the resistance value R_(H) of the resistance memoryelement, and the impedance between the bit line BL1 and the source lineSL1 is

R _(H) ×R _(IC)/(R _(H) +R _(IC))≈R _(IC).

Then, to the bit line BL1, a negative bias voltage which is the same asa voltage necessary to set the resistance memory element 12 or whoseabsolute value is a little larger than the voltage is applied. Thus, acurrent path to the source line SL1 via the bit line BL1, the resistancememory element 12 and the cell select transistor 14 is formed, and theapplied bias voltage is divided to resistance memory element 12 and thecell select transistor 14, corresponding to the resistance value R_(H)of the resistance memory element 12 and the channel resistance R_(CS) ofthe cell select transistor 14.

At this time, because of the resistance value R_(H) of the resistancememory element 12, which is sufficiently large in comparison with thechannel resistance R_(CS) of the cell select transistor, most of thebias voltage is applied to the resistance memory element 12. Thus, theresistance memory element 12 is changed from the high resistance stateto the low resistance state.

Then, the bias voltage to be applied to the bit line BL1 is returned tozero, and then the voltage to be applied to the gate terminal of theimpedance control transistor 16 and the voltage to be applied to theword line WL1 are turned off. Thus, the setting operation is completed.

Next, the rewriting operation from the low resistance state to the highresistance state, i.e., the resetting operation will be explained. Thememory cell 10 to be written is a memory cell 10 connected to the wordline WL1 and the bit line BL1.

First, a prescribed voltage is applied to the gate terminal of theimpedance control transistor 16 to turn on the impedance controltransistor 16. At this time, the channel resistance R_(IC) of theimpedance control transistor 16 is controlled by the voltage applied tothe gate terminal to thereby make an impedance as seen from the outsideof the memory cell, i.e., an impedance between the bit line BL and thesource line SL not more than a resistance value R_(L) of the resistancememory element 12 in the low resistance state. The impedance as seenfrom the outside of the memory cell can be set not more than theresistance value R_(L) of the resistance memory element 12 in the lowresistance state by setting the channel resistance R_(IC) of theimpedance control transistor 16 not more than the resistance value R_(L)of the resistance memory element 12 in the low resistance state.

To approximate the impedance of the memory cell with the resistancememory element 12 in the low resistance state to the impedance of thememory cell with the resistance memory element 12 in the high resistancestate, it is preferable to control the channel resistance R_(IC) of theimpedance control transistor 16 to be much smaller than the resistancevalue R_(L) of the resistance memory element 12 in the low resistancestate, preferably not more than ½, more preferably not more than ⅕,further more preferably not more than 1/10.

Concurrently with turning on the impedance control transistor 16, aprescribed voltage is applied to the word line WL1 to turn on the cellselect transistor 14. At this time, the voltage to be applied to theword line WL1 is controlled so that the channel resistance R_(CS) of thecell select transistor 14 is ignorably small in comparison with theresistance value R_(L) of the resistance memory element 12 in the lowresistance state.

The source line SL1 is connected to a reference potential, e.g., 0 V,which is the ground potential.

The applied voltages to the impedance control transistor 16 and to thecell select transistor 14 are thus set, whereby the channel resistanceR_(IC) of the impedance control transistor 16 is ignorably small incomparison with the resistance value R_(L) of the resistance memoryelement, and the impedance between the bit line BL1 and the source lineSL1 is

R _(L) ×R _(IC)/(R _(L) +R _(IC))≈R _(IC).

That is, this impedance value is substantially equal to the impedancebetween the bit line BL1 and the source line SL1 when set.

Then, to the bit line BL1, a positive bias voltage which is the same asa voltage necessary to reset the resistance memory element 12 or whoseabsolute value is a little larger than the voltage is applied. Thus, acurrent path to the source line SL1 via the bit line BL1, the resistancememory element 12 and the cell select transistor 14 is formed, and theapplied bias voltage is divided to the resistance memory element 12 andthe cell select transistor 14, corresponding to the resistance valueR_(L) of the resistance memory element 12 and the channel resistanceR_(CS) of the cell select transistor 14.

At this time, because of the channel resistance R_(CS) of the cellselect transistor 14 which is sufficiently smaller than the resistancevalue R_(L) of the resistance memory element 12, most of the appliedbias voltage is applied to the resistance memory element 12. Thus, theresistance memory element 12 is changed from the low resistance state tothe high resistance state.

In the case that the bipolar resistance memory material is used, thepolarity of the voltage necessary for the setting and the polarity ofthe voltage necessary for the resetting are different from each other, aset value of the voltage to be applied in the resetting process can bedecided independently of a set value of the voltage to be applied in thesetting process.

Next, the bias voltage to be applied to the bit line BL1 is returned tozero, and then the voltage to be applied to the gate terminal of theimpedance control transistor 16 and the voltage to be applied to theword line WL are turned off. Thus, the resetting operation is completed.

In the nonvolatile semiconductor memory device according to the presentembodiment, in the resetting operation described above, by concurrentlydriving a plurality of bit lines BL (e.g., BL1-BL4), a plurality of thememory cells 10 connected to a selected word line (e.g., WL1) can bereset at once.

Next, the method of reading the nonvolatile semiconductor memory deviceaccording to the present embodiment will be explained. A memory cell 10to be read is the memory cell 10 connected to the word line WL1 and thebit line BL1.

First, a prescribed voltage is applied to the word line WL1 to turn onthe cell select transistor 14. At this time, the voltage to be appliedto the word line WL1 is controlled so that a channel resistance R_(CS)of the cell select transistor 14 is sufficiently smaller than aresistance value R_(L) of the resistance memory element 12 in the lowresistance state.

In the reading operation of the nonvolatile semiconductor memory deviceaccording to the present embodiment, the impedance control transistor 16is not used. That is, the impedance control transistor 16 is turned off.

The source line SL1 is connected to a reference voltage, e.g., 0 V,which is the ground potential.

Then, to the bit line BL1, a prescribed bias voltage which does notcause the setting and the resetting is applied. When the resistancememory element 12 has the current-voltage characteristics of, e.g., FIG.2, the bias voltage is set so that a voltage of not more than about 1.0V is applied to the resistance memory element 12.

When such bias voltage is applied to the bit line BL1, a currentcorresponding to the resistance value of the resistance memory element12 flows in the bit line BL1. A value of the current flowing in the bitline BL1 is detected, whereby a resistance state of the resistancememory element 12 can be read.

As described above, according to the present embodiment, the impedancecontrol transistor is provided, parallelly connected to the resistancememory element, and in a rewriting, the resistance value of theimpedance control transistor is sufficiently smaller than the resistancevalue of the resistance memory elements in the low resistance state,whereby the impedance as seen from the outside of the memory cell can bemade substantially equal in a rewriting, irrespective of resistancesstates of the resistance memory element. Thus, both when the memory cellis rewritten from the high resistance state to the low resistance andwhen the memory cells are rewritten from the low resistance state to thehigh resistance state, the impedance matching can be made between theperipheral circuit and the memory cell.

A Third Embodiment

The nonvolatile semiconductor memory device, a method of writing intothe same and the method of reading the same according to a thirdembodiment of the present invention will be explained with reference toFIGS. 10 and 11. The same members of the present embodiment as those ofthe nonvolatile semiconductor memory device, a method of writing intothe same and the method of reading the same according to the firstembodiment shown in FIGS. 1 to 9 are represented by the same referencenumbers not to repeat or to simplify their explanation.

FIGS. 10 and 11 are circuit diagrams showing the structure of thenonvolatile semiconductor memory device according to the presentembodiment.

First, the structure of the nonvolatile semiconductor memory deviceaccording to the present embodiment will be explained with reference toFIGS. 10 and 11.

A memory cell 10 of the nonvolatile semiconductor memory deviceaccording to the present embodiment includes, as shown in FIG. 10, aresistance memory element 12, a cell select transistor 14 and animpedance control transistor 16. The resistance memory element 12 andthe impedance control transistor 16 are parallelly connected, and thisparallelly connected set has one end connect to the bit line BL and theother end connected to the drain terminal of the cell select transistor14. The cell select transistor 14 has the source terminal connected tothe source line SL and the gate terminal connected to the word line WL.The impedance control transistor 16 has the gate terminal connected tothe control line CL.

The resistance memory element 12 includes a resistance memory materialsandwiched between a pair of electrodes. The resistance memory materialmay be either of the bipolar resistance memory material and the unipolarresistance memory material. In the present embodiment, the resistancememory material is, e.g., the unipolar resistance memory material of,e.g., TiO_(x).

FIG. 11 is a circuit diagram of the memory cell array of the memorycells 10 shown in FIG. 10 arranged in a matrix. The memory cells 10 areformed adjacent to each other in the column direction (vertically in thedrawing) and the row direction (horizontally in the drawing).

In the column direction, a plurality of word lines WL1, /WL1, WL2, /WL2. . . , control lines CL1, /CL1, CL2, /CL2 . . . and source lines SL1,SL2 . . . are arranged to respectively form signal lines common amongthe memory cells 10 arranged in the row direction. The source lines SLare provided each for two word lines WL.

A plurality of bit lines BL1, BL2, BL3, BL4 . . . are arranged in therow direction (horizontally in the drawing) to form signal lines commonamong the memory cells 10 arrange din the row direction.

Next, the method of writing into the nonvolatile semiconductor memorydevice according to the present embodiment shown in FIG. 11 will beexplained with reference to FIGS. 7 and 8.

First, the rewriting operation from the high resistance state to the lowresistance state, i.e., the setting operation will be explained withreference to FIG. 7. A memory cell to be rewritten is the memory cell 10connected to the word line WL1 and the bit line BL1.

First, a prescribed voltage is applied to the control line CL1 to turnon the impedance control transistor 16 (see FIG. 7). At this time, thechannel resistance R_(IC) of the impedance control transistor 16 iscontrolled by the voltage applied to the control line CL1 to therebymake an impedance as seen from the outside of the memory cell, i.e., animpedance between the bit line BL and the source line SL not more than aresistance value R_(L) of the resistance memory element 12 in the lowresistance state.

Concurrently with turning on the impedance control transistor 16, aprescribed voltage is applied to the word line WL1 to turn on the cellselect transistor 14 (see FIG. 7). At this time, the voltage to beapplied to the word line WL1 is controlled to be a value which isignorably small in comparison with a synthetic resistance(R_(H)×R_(IC)/(R_(H)+R_(IC))) of a resistance value R_(H) of theresistance memory element 12 in the high resistance and a channelresistance R_(IC) of the impedance control transistor 16.

At this time the impedance as seen from the outside of the memory cellcan be set substantially not more than the resistance value R_(L) of theresistance memory element 12 in the low resistance state by setting thechannel resistance R_(IC) of the impedance control transistor 16 notmore than the resistance value R_(L) of the resistance memory element 12in the low resistance state.

To approximate the impedance of the memory cell with the resistancememory element 12 in the low resistance state to the impedance of thememory cell with the resistance memory element 12 in the high resistancestate, it is preferable to control the channel resistance R_(IC) of theimpedance control transistor 16 to be much smaller than the resistancevalue R_(L) of the resistance memory element 12 in the low resistancestate, preferably not more than ½, more preferably not more than ⅕,further more preferably not more than 1/10.

The source line SL1 is connected to a reference potential, e.g., 0 V,which is the ground potential (see FIG. 7).

The voltage to be applied to the impedance control transistor 16 and thecell select transistor 14 are so set, whereby the channel resistanceR_(IC) of the impedance control transistor 16 is ignorably small incomparison with the resistance value R_(H) of the resistance memoryelement 12, and the resistance value R_(CS) of the cell selecttransistor 14 is ignorably small in comparison with the syntheticresistance (R_(H)×R_(IC)/(R_(H)+R_(IC))) of the resistance value R_(H)of the resistance memory element 12 and the channel resistance R_(IC) ofthe impedance control transistor 16, and the impedance between the bitline BL1 and source line SL1 is

[R _(H) ×R _(IC)/(R _(H) +R _(IC))]+R _(CS) ≈R _(IC).

Then, a bias voltage which is the same as or a little higher than thevoltage necessary to set the resistance memory element 12 is applied tothe bit line BL1 (see FIG. 7). Thus, a current path to the source lineSL1 via the bit line BL1, the resistance memory element 12 and the cellselect transistor 14 is formed, and the applied bias voltage is dividedto the resistance memory element 12 and the cell select transistor 14respectively corresponding to the synthetic resistance(R_(H)×R_(IC)/(R_(H)+R_(IC))) of the resistance value R_(H) of theresistance memory element 12 and the channel resistance R_(IC) of theimpedance control transistor 16, and the channel resistance R_(CS) ofthe cell select transistor 14.

At this time, because of the synthetic resistance(R_(H)×R_(IC)/(R_(H)+R_(IC))) of the resistance value R_(H) of theresistance memory element 12 and the channel resistance R_(IC) of theimpedance control transistor 16, which is sufficiently large incomparison with the resistance R_(CS) of the cell select transistor 14,most of the bias voltage is applied to the resistance memory element 12.Thus, the resistance memory element 12 is changed from the highresistance state to the lower resistance state.

Then, the bias voltage to be applied to the bit line BL1 is returned tozero, and then the voltage to be applied to the control line CL1 and thevoltage to be applied to the word line WL1 are turned off. Thus, thesetting operation is completed (see FIG. 7).

Then, the rewriting operation from the low resistance state to the highresistance state, i.e., the resetting operation will be explained withreference to FIG. 8. A memory cell to be rewritten is the memory cell 10connected to the word line WL1 and the bit line BL1.

First, a prescribed voltage is applied to the control line CL1 to turnon the impedance control transistor 16 (see FIG. 8). At this time, thechannel resistance R_(IC) of the impedance control transistor 16 iscontrolled by the voltage applied to the control line CL1 to therebymake the impedance as seen from the outside of the memory cell, i.e.,the impedance between the bit line BL and the source line SL not morethan the resistance value R_(L) of the resistance memory element 12 inthe low resistance state.

Concurrently with turning on the impedance control transistor 16, aprescribed voltage is applied to the word line WL1 to turn on the cellselect transistor 14 (see FIG. 8). At this time, the voltage to beapplied to the word line WL1 is controlled so that the channelresistance R_(CS) of the cell select transistor 14 is ignorably small incomparison with the synthetic resistance (R_(L)×R_(IC)/(R_(L)+R_(IC)))of the resistance value R_(L) OF the resistance memory element 12 in thelow resistance state and the channel resistance R_(IC) of the impedancecontrol transistor 16.

At this time, the impedance as seen from the outside of the memory cellcan be set substantially not more than the resistance value R_(L) of theresistance memory element 12 in the low resistance state by setting thechannel resistance of the impedance control transistor 16 not more thanthe resistance value R_(L) of the resistance memory element 12 in thelow resistance state.

To approximate the impedance of the memory cell with the resistancememory element 12 in the low resistance state to the impedance of thememory cell with the resistance memory element 12 in the high resistancestate, preferably, the channel resistance R_(IC) of the impedancecontrol transistor 16 is controlled to be sufficiently smaller than theresistance value R_(L) of the resistance memory element 12 in the lowresistance state, preferably not more than ½, more preferably not morethan ⅕ and further more preferably not more than 1/10.

The source line SL1 is connected to a reference potential, e.g., 0 V,which is the ground potential (see FIG. 8).

The applied voltage to the impedance control transistor 16 and the cellselect transistor 14 are thus set, whereby the channel resistance R_(IC)of the impedance control transistor 16 is ignorably small in comparisonwith the resistance value R_(L) of the resistance memory element 12, andthe channel resistance R_(CS) of the cell select transistor 14 isignorably small in comparison with the synthetic resistance(R_(L)×R_(IC)/(R_(L)+R_(IC))) of the resistance value R_(L) of theresistance memory element 12 and the channel resistance R_(IC) of theimpedance control transistor 16, and the impedance between the bit lineBL1 and the source line SL1 is

[R _(L) ×R _(IC)/(R _(L) +R _(IC))]+R _(CS) ≈R _(IC).

That is, this impedance value is substantially equal to the impedancebetween the bit line BL1 and the source SL1 when set.

Then, a bias voltage which is the same or a little higher than thevoltage necessary to set the resistance memory element 12 is applied tothe bit line BL1 (see FIG. 8). Thus, a current path to the source lineSL1 via the bit line BL1, the resistance memory element 12 and the cellselect transistor 14 is formed, and the applied bias voltage is dividedto the resistance memory element 12 and the cell select transistor 14respectively corresponding to the synthetic resistance(R_(L)×R_(IC)/(R_(L)+R_(IC))) of the resistance value R_(L) of theresistance memory element 12 and the channel resistance R_(IC) of theimpedance control transistor 16, and the channel resistance R_(CS) ofthe cell select transistor 14.

At this time, because of the channel resistance R_(IC) of the cellselect transistor 14 which is sufficiently smaller than the syntheticresistance (R_(L)×R_(IC)/(R_(L)+R_(IC))) of the resistance value R_(L)of the resistance memory element 12 and the channel resistance R_(IC) ofthe impedance control transistor 16, most the applied bias voltage isapplied to the resistance memory element 12. Thus, the resistance memoryelement 12 is changed from the low resistance state to the highresistance state.

In the resetting process, as described above, at the instance when theresistance memory element 12 has been changed to the high resistancestate, almost all the bias voltage is divided to the resistance memoryelement 12. Accordingly, it is necessary to prevent the resistancememory element 12 from being reset by this bias voltage. To this end,the bias voltage to be applied to the bit line BL must be smaller thanthe voltage necessary for the setting.

That is, in the resetting process, the channel resistance R_(CS) of thecell select transistor 14 is adjusted to be sufficiently smaller thanthe synthetic resistance (R_(L)×R_(IC)/(R_(L)+R_(IC))) of the resistancevalue R_(L) of the resistance memory element 12 and the channelresistance R_(IC) of the impedance control transistor 16 while the biasvoltage to be applied to the bit line BL is set to be not less than thevoltage necessary for the resetting and less than the voltage necessaryfor the setting.

Then, the bias voltage to be applied to the bit line BL1 is returned tozero, and then the voltage to be applied to the control line CL1 and thevoltage to be applied to the word line WL1 are turned off. Thus, theresetting operation is completed (see FIG. 8B.

In the nonvolatile semiconductor memory device according to the presentembodiment, a plurality of bit lines BL (e.g., BL1-BL4) are concurrentlydriven in the resetting operation described above, whereby a pluralityof memory cells 10 connected to the selected word line (e.g., WL1) canbe reset at once.

Next, the method of reading the nonvolatile semiconductor memory deviceaccording to the present embodiment shown in FIG. 11 will be explainedwith reference to FIG. 9. A memory cell 10 to be read is the memory cell10 connected to the word line WL1 and the bit line BL1.

First, a prescribed voltage is applied to the word line WL1 to turn onthe cell select transistor 14 (see FIG. 9). At this time, the voltage tobe applied to the word line WL1 is controlled so that the channelresistance R_(CS) of the cell select transistor 14 is sufficientlysmaller than the resistance value R_(L) of the resistance memory element12 in the low resistance state.

The impedance control transistor 16 is not used in the reading operationof the nonvolatile semiconductor memory device according to the presentembodiment. That is, the impedance control transistor 16 is off (seeFIG. 9).

The source line SL1 is connected to a reference potential, e.g., 0 V,which is the ground potential (see FIG. 8).

Then, a prescribed bias voltage which does not cause the setting and theresetting is applied to the bit line BL1 (see FIG. 9). When theresistance memory element 12 has, e.g., the current-voltagecharacteristics shown in FIG. 2, the bias voltage is set so that avoltage not more than about 1.0 V is applied to the resistance memoryelement 12.

When the bias voltage is applied to the bit line BL1, currentcorresponding to the resistance memory element 12 flows in the bit lineBL1. Accordingly, the value of the current flowing in the bit line BL1is detected, whereby the resistance state of the resistance memoryelement 12 can be read.

As described above, according to the present embodiment, the impedancecontrol transistor is provided, parallelly connected to the resistancememory element, and in the rewriting, the resistance value of theimpedance control transistor is made sufficiently smaller than theresistance value of the resistance memory elements in the lowresistance, whereby irrespective of the resistance state of theresistance memory elements, the impedance as seen from the outside ofthe memory cell in the rewriting can be made substantially equal. Thus,both when the memory cell is rewritten from the high resistance state tothe low resistance state and when the memory cell is rewritten from thelow resistance state to the high resistance state, the impedancematching can be made between the peripheral circuit and the memory cell.

A Fourth Embodiment

The nonvolatile semiconductor memory device, the method of writing intothe same and the method of reading the same according to a fourthembodiment of the present invention will be explained. The same membersof the present embodiment as those of the nonvolatile semiconductormemory device the method of writing into the same and the method ofreading the same according to the third embodiment are represented bythe same reference numbers not to repeat or to simplify theirexplanation.

The nonvolatile semiconductor memory device according to the presentembodiment is the same as the nonvolatile semiconductor memory deviceaccording to the third embodiment shown in FIGS. 10 and 11 except thatin the former, the resistance memory element 12 is formed of the bipolarresistance memory material. The bipolar resistance memory material canbe, e.g., Cr-doped SrZrO₃, etc. In the resistance memory element of thenonvolatile semiconductor memory device according to the presentembodiment, as shown in, e.g., FIG. 1, a negative bias voltage isapplied in the setting, and in the resetting, a positive bias voltage isapplied.

Next, the method of writing into the nonvolatile semiconductor memorydevice according to the present embodiment will be explained. The methodof writing into the nonvolatile semiconductor memory device according tothe present embodiment is basically the same as the method of writinginto the nonvolatile semiconductor memory device according to the firstembodiment except the polarity of the bias voltage.

First, the rewriting operation from the high resistance state to the lowresistance state, i.e., the setting operation will be explained. Amemory cell 10 to be rewritten is the memory cell 10 connected to theword line WL1 and the bit line BL1.

First, a prescribed voltage is applied to the control line CL1 to turnon the impedance control transistor 16. At this time, the channelresistance R_(IC) of the impedance control transistor 16 is controlledby the voltage applied to the control line CL1 to thereby make animpedance as seen from the outside of the memory cell, i.e., animpedance between the bit line BL and the source line SL not more than aresistance value R_(L) of the resistance memory element 12 in the lowresistance state.

Concurrently with turning on the impedance control transistor 16, aprescribed voltage is applied to the word line WL1 to turn on the cellselect transistor 14. At this time, the voltage to be applied to theword line WL1 is controlled so that the channel resistance R_(CS) of thecell select transistor 14 is ignorably small in comparison with thesynthetic resistance (R_(H)×R_(IC)/(R_(H)+R_(IC))) of the resistancevalue R_(H) of the resistance memory element 12 in the high resistancestate and the channel resistance R_(IC) of the impedance controltransistor 16.

At this time, the impedance as seen from the outside of the memory cellcan be set substantially not more than the resistance value R_(L) of thememory cell element 12 in the low resistance state by setting thechannel resistance R_(IC) of the impedance control transistor 16 notmore than the resistance value R_(L) of the resistance memory element 12in the low resistance state.

To approximate the impedance of the memory cell with the resistancememory element 12 in the low resistance state to the impedance of thememory cell with the resistance memory element 12 in the high resistancestate, preferably, the channel resistance R_(IC) of the impedancecontrol transistor 16 is controlled to be sufficiently smaller than theresistance value R_(L) of the resistance memory element 12 in the lowresistance state, preferably not more than ½, more preferably not morethan ⅕ and further more preferably not more than 1/10.

The source line SL1 is connected to a reference potential, e.g., 0 V,which is the ground potential.

The voltages to be applied to the impedance control transistor 16 andthe cell select transistor 14 are so set, whereby the channel resistanceR_(IC) of the impedance control transistor 16 is ignorably small incomparison with the resistance value R_(H) of the resistance memoryelement 12, and the resistance value R_(CS) of the cell selecttransistor 14 is ignorably small in comparison with the syntheticresistance (R_(H)×R_(IC)/(R_(H)+R_(IC))) of the resistance value R_(H)of the resistance memory element 12 and the channel resistance R_(IC) ofthe impedance control transistor 16, and the impedance between the bitline BL1 and source line SL1 is

[R _(H) ×R _(IC)/(R _(H) +R _(IC))]+R _(CS) ≈R _(IC).

Then, to the bit line BL1, a negative bias voltage which is the same asa voltage necessary to set the resistance memory element 12 or whoseabsolute value is a little larger than the voltage is applied. Thus, acurrent path to the source line SL1 via the bit line BL1, the resistancememory element 12 and the cell select transistor 14 is formed, and theapplied bias voltage is divided to the resistance memory element 12 andthe cell select transistor 14 respectively corresponding to thesynthetic resistance (R_(H)×R_(IC)/(R_(H)+R_(IC))) of the resistancevalue R_(H) of the resistance memory element 12 and the channelresistance R_(IC) of the impedance control transistor 16, and thechannel resistance R_(CS) of the cell select transistor 14.

At this time, because of the synthetic resistance(R_(H)×R_(IC)/(R_(H)+R_(IC))) of the resistance value R_(H) of theresistance memory element 12 and the channel resistance R_(IC) of theimpedance control transistor 16 which is sufficiently large incomparison with the channel resistance R_(CS) of the cell selecttransistor 14, most of the bias voltage is applied to the resistancememory element 12. Thus, the resistance memory element 12 is changedfrom the high resistance state to the low resistance state.

Next, the bias voltage to be applied to the bit line BL1 is returned tozero, and then the voltage to be applied to the control line CL1 and thevoltage to be applied to the word line WL1 are turned off, and thesetting operation is completed.

Then, the rewriting operation from the low resistance state to the highresistance state, i.e., the resetting operation will be explained. Amemory cell to be rewritten is the memory cell connected to the wordline WL1 and the bit line BL1.

First, a prescribed voltage is applied to the control line CL1 to turnon the impedance control transistor 16. At this time, the channelresistance R_(IC) of the impedance control transistor 16 is controlledby the voltage applied to the control line CL1, whereby the impedance asseen from the outside of the memory cell, i.e., the impedance betweenthe bit line BL and the source line SL is not more than the resistancevalue R_(L) of the resistance memory element 12 in the low resistancestate.

Concurrently with turning on the impedance control transistor 16, aprescribed voltage is applied to the word line WL1 to turn on the cellselect transistor 14. At this time, the voltage to be applied to theword line WL1 is controlled so that the channel resistance R_(CS) of thecell select transistor 14 is ignorably small in comparison with thesynthetic resistance (R_(L)×R_(IC)/(R_(L)+R_(IC))) of the resistancevalue R_(L) of the resistance memory element 12 in the low resistancestate and the channel resistance R_(IC) of the impedance controltransistor 16.

At this time, the impedance as seen from the outside of the memory cellcan be set substantially not more than the resistance value R_(L) of theresistance memory element 12 in the low resistance state by setting thechannel resistance R_(IC) of the resistance memory element 12 not morethan the resistance value R_(L) of the resistance memory element 12 inthe low resistance state.

To approximate the impedance of the memory cell with the resistancememory element 12 in the low resistance state to the impedance of thememory cell of the resistance memory element 12 in the high resistancestate, preferably, the channel resistance R_(IC) of the impedancecontrol transistor 16 is controlled to be sufficiently smaller than theresistance value R_(L) of the resistance memory element 12 in the lowresistance state, preferably not more than ½, more preferably not morethan ⅕ and further more preferably not more than 1/10.

The source line SL1 is connected to a reference potential, e.g., 0 V,which is the ground potential.

The applied voltages to the impedance control transistor 16 and the cellselect transistor 14 are thus set, whereby the channel resistance R_(IC)of the impedance control transistor 16 is ignorably small in comparisonwith the resistance value R_(L) of the resistance memory element 12, andthe channel resistance R_(CS) of the cell select transistor 14 isignorably small in comparison with the synthetic resistance(R_(L)×R_(IC)/(R_(L)+R_(IC))) of the resistance value R_(L) of theresistance memory element 12 and the channel resistance R_(IC) of cellselect transistor 16, and the impedance between the bit line BL1 and thesource line SL1 is

[R _(L) ×R _(IC)/(R _(L) +R _(IC))]+R _(CS) ≈R _(IC).

That is, this impedance value is substantially equal to the impedancebetween the bit line BL1 and the source line SL1 when set.

Then, to the bit line BL1, a positive bias voltage which is the same asa voltage necessary for resetting the resistance memory element 12 orwhose absolute value is a little larger than the voltage is applied.Thus, a current path to the source line SL1 via the bit line BL1, theresistance memory element 12 and the cell select transistor 14 isformed, and the applied voltage is divided to the resistance memoryelement 12 and the cell select transistor 14 respectively correspondingto the synthetic resistance (R_(L)×R_(IC)/(R_(L)+R_(IC))) of theresistance value R_(L) of the resistance memory element 12 and thechannel resistance R_(IC) of the impedance control transistor 16, andthe channel resistance R_(CS) of the cell select transistor 14.

At this time, because of the channel resistance R_(CS) of the cellselect transistor 14 which is sufficiently smaller than the resistancevalue R_(L) of the resistance memory element 12, most of the appliedbias voltage is applied to the resistance memory element 12. Thus, theresistance memory element 12 is changed form the low resistance state tothe high resistance state.

In the case that the bipolar resistance memory material is used, thepolarity of the voltage necessary for the setting and the polarity ofthe voltage necessary for the resetting are different from each other,which allows the set value of the voltage to be applied in the resettingprocess can be set independent of the set value of the voltage to beapplied in the setting process.

Then, the bias voltage to be applied to the bit line BL1 is returned tozero, and then the voltage to be applied to the control line CL1 and thevoltage to be applied to the word line WL1 are turned off. Thus, theresetting operation is completed.

In the nonvolatile semiconductor memory device according to the presentembodiment, in the resetting operation described above, a plurality ofbit lines BL (e.g., BL1-BL4) are concurrently driven, whereby aplurality of memory cells connected to the selected word line (e.g.,WL1) can be reset at once.

Next, the method of reading the nonvolatile semiconductor memory deviceaccording to the present embodiment will be explained. A memory cell 10to be read is the memory cell 10 connected to the word line WL1 and thebit line BL1.

First, a prescribed voltage is applied to the word line WL1 to turn onthe cell select transistor 14. At this time, the voltage to be appliedto the word line WL1 is controlled so that the channel resistance R_(CS)of the cell select transistor 14 is sufficiently smaller than theresistance value R_(L) of the resistance memory element 12 in the lowresistance state.

In the reading operation of the nonvolatile semiconductor memory deviceaccording to the present embodiment, the impedance control transistor 16is not used. That is, the impedance control transistor 16 is turned off.

The source line SL1 is connected to a reference potential, i.e., 0 V,which is the ground potential.

Next, to the bit line BL1, a prescribed bias voltage which causesneither the setting nor the resetting is applied. In the case that theresistance memory element 12 has the current-voltage characteristicsshown in, e.g., FIG. 2, the bias voltage is set so that a voltage of notmore than about 1.0 V is applied to the resistance memory element 12.

When such bias voltage is applied to the bit line BL1, currentcorresponding to the resistance value of the resistance memory element12 flows in the bit line BL1. Accordingly, the value of the currentflowing in the bit line BL1 is detected, whereby the resistance state ofthe resistance memory element 12 can be read.

As described above, according to the present embodiment, the impedancecontrol transistor is provided, parallelly connected to the resistancememory element, and in the resetting, the resistance value of theimpedance control transistor is made sufficiently smaller than theresistance value of the resistance memory elements in the low resistancestate, whereby independently of the resistance state of the resistancememory element, in the rewriting, the impedance as seen from the outsideof the memory cell can be made substantially the same. Thus, both whenthe memory cell is rewritten from the high resistance state to the lowresistance state and when the memory cell is rewritten from the lowresistance state to the high resistance state, the impedance matchingcan be easily made between the peripheral circuit and the memory cell.

A Fifth Embodiment

The nonvolatile semiconductor memory device, the method of writing intothe same and the method of reading the same according to a fifthembodiment of the present invention will be explained with reference toFIG. 12. The same members of the present embodiment as those of thenonvolatile semiconductor memory device, the method of writing into thesame and the method of reading the same according to the first to thefourth embodiments shown in FIGS. 1 to 11 are represented by the samereference numbers not to repeat or to simplify their explanation.

FIG. 12 is a circuit diagram showing the structure of the nonvolatilesemiconductor memory device according to the present embodiment.

In the first and the second embodiments, the channel resistance R_(IC)of the impedance control transistor 16 is controlled for controlling thecurrent flowing in the bit line BL, but the method for controlling thecurrent flowing in the bit line BL is not limited to this method. Forexample, the circuit shown in FIG. 12 may be provided in place of theimpedance control transistor 16 shown in FIG. 6.

The circuit shown in FIG. 12 includes a plurality of serially connectedsets each including a resistor r and a select transistor Tr, which areparallelly arranged. The resistance values of the resistors r₁, r₂, . .. , r_(n) are set suitably corresponding to the writing/readingcharacteristics of the nonvolatile semiconductor memory device.

In the circuit shown in FIG. 12, at least one of the select transistorsTr₁, Tr₂, . . . , Tr_(n) is turned on, whereby the resistors r₁, r₂, . .. , r_(n) are serially connected to the bit line BL. The impedance ofthe memory cell can be changed only by switching the select transistorsTr₁, Tr₂, . . . , Tr_(n) to be turned on, which facilitates the controlin comparison with controlling the channel resistance R_(IC) of theimpedance control transistor 16.

Two or more of the select transistors Tr may be turned on at once. Forexample, in the circuit including the resistor r₁ and the resistor r₂,the resistance value with the select transistor Tr₁ turned on is r₁, andthe resistance value with the select transistor Tr₂ turned on is r₂. Theresistance value with the select transistors Tr₁, Tr₂ turned on at onceis r₁r₂/(r₁+r₂). Accordingly, the select transistors Tr to be turned onare suitably combined, whereby more resistance states can be realized,which can simplify the circuit structure.

As described above, according to the present embodiment, the impedanceof the memory cell can be easily controlled. Thus, the impedancemismatching in the setting and resetting can be mitigated.

A Sixth Embodiment

The nonvolatile semiconductor memory device and the method ofmanufacturing the same according to a sixth embodiment of the presentinvention will be explained with reference to FIGS. 13 to 15E.

FIG. 13 is a plan view showing the structure of the nonvolatilesemiconductor memory device according to the present embodiment. FIG. 14is a diagrammatic sectional view showing the structure of thenonvolatile semiconductor memory device according to the presentembodiment. FIGS. 15A-15E are sectional views showing the method ofmanufacturing the nonvolatile semiconductor memory device according tothe present embodiment.

In the present embodiment, the specific structure of the nonvolatilesemiconductor memory device according to the third embodiment describedabove, and the method of manufacturing the same will be explained.

First, the structure of the nonvolatile semiconductor memory deviceaccording to the present embodiment will be explained with reference toFIGS. 13 and 14.

In a silicon substrate 20, a device isolation film 22 for definingdevice regions is formed. In the device regions in the silicon substrate20, cell select transistors each including a gate electrode 24 andsource/drain regions 26, 28, and current control transistors eachincluding a gate electrode 30 and source/drain regions 28, 32 areformed.

As shown in FIG. 13, the gate electrodes 24 function also as word linesWL and the gate electrodes 24 of the cell select transistors adjacentcolumn-wise are commonly connected to, and the gate electrodes 30function also as control lines CL and the gate electrodes 30 of thecolumn-wise adjacent impedance control transistors are commonlyconnected to.

Over the silicon substrate 10 with the cell select transistors and thecurrent control transistors formed on, an inter-layer insulating film 34with contact plugs 36 electrically connected to the source/drain regions26, contact plugs 38 electrically connected to the source/drain regions28 and contact plugs 40 electrically connected to the source/drainregions 32 buried in is formed.

On the inter-layer insulating film 34 with the contact plugs 36, 38, 40buried in, source lines 42 electrically connected to the source/drainregions 26 via the contact plugs 36 and resistance memory elements 50electrically connected to the source/drain regions 28 via the contactplugs 38 are formed.

Over the inter-layer insulating film 34 with the source lines 42 and theresistance memory elements 50 formed on, an inter-layer insulating film52 with contact plugs 54 electrically connected to the resistance memoryelements 50 and contact plugs 56 electrically connected to the contactplugs 40 buried in is formed.

On the inter-layer insulating film 52 with the contact plugs 54, 56buried in, bit lines 58 electrically connected to the source/drainregions 32 via the contact plugs 56, 40 are formed.

Thus, the nonvolatile semiconductor memory device according to the thirdembodiment shown in FIG. 11 is constituted.

Next, the method of manufacturing the nonvolatile semiconductor memorydevice according to the present embodiment will be explained withreference to FIGS. 15A to 16B.

First, the device isolation film 22 for defining the device regions isformed in the silicon substrate 20 by, e.g., STI (Shallow TrenchIsolation) method.

Then, in the device regions of the silicon substrate 20, in the same wayas in the method of manufacturing the usual MOS transistor, the cellselect transistors each including the gate electrode 24 and thesource/drain regions 26, 28 and the impedance control transistors eachincluding the gate electrode 30 and the source/drain regions 28, 32 areformed (FIG. 15A). The source/drain regions 28 are common among the cellselect transistors ad the impedance control transistors.

Over the silicon substrate 20 with the cell select transistors and thecurrent control transistors formed on, a silicon oxide film is depositedby, e.g., CVD method to form the inter-layer insulating film 34 of thesilicon oxide film.

Then, by lithography and dry etching, contact holes down to thesource/drain regions 26, 28, 32 are formed in the inter-layer insulatingfilm 34.

Next, a barrier metal and a tungsten film are deposited by, e.g., CVDmethod, and then these conductive films are etched back to form in theinter-layer insulating film 34 the contact plugs 36, 38, 40 electricallyconnected to the source/drain regions 26, 28, 32 (FIG. 15B).

Then, on the inter-layer insulating film 34 with the contact plugs 36,38, 40 buried in, the source lines 42 electrically connected to thesource/drain regions 26 via the contact plugs 36 and the resistancememory elements 50 electrically connected to the source/drain regions 28via the contact plugs 38 are formed (FIG. 15C).

The resistance memory elements 50 each includes a lower electrode 44connected to the contact plug 38, a resistance memory material layer 46formed on the lower electrode 44 and an upper electrode 48 formed on theresistance memory material layer 46.

In the case that the resistance memory material layer 46 is formed ofthe bipolar resistance memory material, for example, Pr_(1-x)Ca_(x)MnO₃(x≦1), La_(1-x)Ca_(x)MnO₃ (x≦1), and SrTiO₃ or SrZrO₃ doped with Cr, Nbor others is formed by laser ablation, sol-gel, sputtering, MOCVD orother methods. In the case that the resistance memory material 46 isformed of the unipolar resistance memory material, for example, NiO_(y)(y≦1), TiO_(z) (z≦2), HfO_(z) (z≦2) or others is formed by sol-gel,sputtering, MOCVD or other methods.

Then, over the inter-layer insulating film 34 with the source lines 42and the resistance memory elements 50 formed on, a silicon oxide film isdeposited by, e.g., CVD method to form the inter-layer insulating film52 of the silicon oxide film.

Then, by lithography and dry etching, in the inter-layer insulating film52, the contact holes down to the upper electrodes 48 of the resistancememory elements 50 and the contact holes down to the contact plugs 40are formed.

Next, a barrier metal and a tungsten film are deposited by, e.g., CVDmethod, and then these conductive films are etched back to form in theinter-layer insulating film 32 the contact plugs 54 electricallyconnected to the upper electrodes 48 of the resistance memory elements50 and the contact plugs 56 electrically connected to the contact plugs40 (FIG. 15D).

Then, on the inter-layer insulating film 52 with the contact plugs 54,56 buried in, a conductive film is deposited, and then the conductivefilm is patterned by photolithography and dry etching to form the bitlines 58 electrically connected to the source/drain regions 32 via thecontact plugs 56, 40 (FIG. 15E).

Then, upper level interconnection layers as required are formed thereon,and the nonvolatile semiconductor memory device is completed.

Modified Embodiments

The present invention is not limited to the above-described embodimentsand can cover other various modifications.

For example, in the above-described embodiments, as the unipolarresistance memory material, TiO_(x) is used, and Cr-doped SrZrO₃ is usedas the bipolar resistance memory material. However, the material formingthe resistance memory element is not limited to them. For example, asthe unipolar resistance memory material, NiO_(x), etc. can be used, andas the bipolar resistance memory material, Cr-doped SrTiO₃,Pr_(1-x)Ca_(x)MnO₃, La_(1-x)Ca_(x)MnO₃, etc., which exhibit CMR(Colossal Magneto-Resistance) can be used. In the setting and resetting,it is preferable to set the applied voltages and current limit valuessuitably corresponding to the kinds of the resistance memory material,structures of the resistance memory elements, etc.

In the above-described embodiment, in the setting operation, to make theimpedance as seen from the outside of the memory cell in the settingoperation and the impedance as seen from the outside of the memory cellsin the resetting operation substantially equal to each other, thechannel resistance R_(IC) of the impedance control transistor 16 in thesetting operation and the channel resistance R_(IC) of the impedancecontrol transistor 16 in the resetting operation are set not more thanthe resistance value R_(L) in the low resistance state. However, it isnot essentially necessary to make the impedance as seen from the outsideof the memory cells in the setting operation and the impedance as seenfrom the outside of the memory cells in the resetting operation equal toeach other. The channel resistance R_(IC) of the impedance controltransistor 16 may be suitably set so that in the setting operation, theimpedance as seen from the outside of the memory cell makes theimpedance-matching with the writing circuit, and in the resettingoperation, the impedance as seen from the outside of the memory cellmakes the impedance matching with the writing circuit, respectively.

In terms of the impedance matching with the writing circuit, it isidealistic that the impedance as seen from the outside of the memorycell in the setting operation is equal to the impedance as seen from theoutside of the memory cell in the resetting operation. Actually,however, it is difficult to make the impedance of the memory cell thesame in both operations, and it suffices to approximate the impedance asseen from the outside of the memory cell in the setting operation andthe impedance as seen from the outside of the memory cell in theresetting operation to the impedance of the writing circuit in the rangethat no problems, such as reflections of the writing voltage pulses,etc., are caused to the writing characteristics. The allowable range ofthe deviation from the impedance of the writing circuit is preferablyset suitably depending on pulse widths of the writing voltage pulse,other writing conditions, etc.

In the above-described embodiments, the impedance control transistor 16is driven in the setting operation and the resetting operation. However,the impedance control transistor 16 may be driven only in the settingoperation. In this case, the channel resistance of the impedance controltransistor 16 may be controlled so that the impedance as seen from theoutside of the memory cells in the high resistance state is equal orapproximate to the resistance value R_(L) of the low resistance state.In the resetting operation as well, the impedance control transistor 16is driven to set the resistance value thereof above the resistance valueR_(H) in the high resistance state.

In the above-described embodiments, the source lines SL are arranged inparallel with the word lines WL but may be arranged in parallel with thebit lines BL. For example, in the nonvolatile semiconductor memorydevice according to the third and the fourth embodiments, as shown inFIG. 16, the source lines SL1, SL2, . . . may be extended columndirection between adjacent ones of the memory cells. In FIG. 16, theimpedance control transistor 16 is arranged between the bit lines BL andthe source lines SL, but as shown in FIG. 10, the impedance controltransistor 16 may be parallelly connected to the resistance memoryelements 12.

In the above-described embodiments, one memory cell includes one cellselect transistor and one resistance memory element, but the structureof the memory cell is not limited to this. For example, one memory cellmay include one cell select transistor and two resistance memoryelements or may include two cell select transistors and two resistancememory elements, and these structures are expected to improve thereading margin and produce other advantageous effects.

INDUSTRIAL APPLICABILITY

The nonvolatile semiconductor memory device and the method of writinginto the same according to the present invention can easily make theimpedance-matching with the peripheral circuit and the memory cell bothwhen the resistance memory element is rewritten from the high resistancestate to the low resistance state and is rewritten from the lowresistance state to the high resistance state. Thus, the nonvolatilesemiconductor memory device and the method of writing into the sameaccording to the present invention are very useful to improve thereliability and operation speed of the nonvolatile semiconductor memorydevice.

1. A method of writing into a nonvolatile semiconductor memory deviceincluding a resistance memory element which memorizes a high resistancestate and a low resistance state and switches between the highresistance state and the low resistance state by an application of avoltage, a variable resistor being parallelly connected to theresistance memory element, and when the voltage is applied to resistancememory element to switch the resistance memory element between the highresistance state and the low resistance state, a resistance value of thevariable resistor being set corresponding to a resistance state of theresistance memory element so that a writing circuit for applying thevoltage to the resistance memory element, and a synthetic resistor ofthe resistance memory element and the variable resistor make theimpedance-matching.
 2. The method of writing into a nonvolatilesemiconductor memory device according to claim 1, wherein the variableresistor is a MIS transistor.
 3. The method of writing into anonvolatile semiconductor memory device according to claim 1, whereinthe variable resistor includes a plurality of resistor parallellyconnected, and the resistor connecting to the resistance memory elementis selected to thereby control the resistance values of the variableresistor.
 4. A method of writing into a nonvolatile semiconductor memorydevice including a resistance memory element which memorizes a highresistance state and a low resistance state and switches between thehigh resistance state and the low resistance state by an application ofa voltage, a variable resistor being parallelly connected to theresistance memory element, and when the voltage is applied to resistancememory element to switch the resistance memory element between the highresistance state and the low resistance state, a resistance value of thevariable resistor being set so that a synthetic resistance value of theresistance memory element and the variable resistor is not more than alow resistance value of the low resistance state.
 5. The method ofwriting into a nonvolatile semiconductor memory device according toclaim 4, wherein the resistance value of the variable resistor is set sothat a first synthetic resistance value of the resistance memory elementand the variable resistor at a time when the resistance memory elementis switched from the high resistance state to the low resistance state,and a second synthetic resistance value of the resistance memory elementand the variable resistor at a time when the resistance memory elementis switched from the low resistance state to the high resistance statebecome equal to each other.
 6. The method of writing into a nonvolatilesemiconductor memory device according to claim 5, wherein when theresistance memory element is written from the high resistance state tothe low resistance state and when the resistance memory element isrewritten from the low resistance state to the high resistance state,the resistance value of the variable resistor is set not more than thelow resistance value of the low resistance state.
 7. The method ofwriting into a nonvolatile semiconductor memory device according toclaim 5, wherein when the resistance memory element is written from thehigh resistance state to the low resistance state, the resistance valueof the variable resistor is made equal to the low resistance value ofthe low resistance state, and when the resistance memory element iswritten from the low resistance state to the high resistance state, theresistance value of the variable resistor is set not less than a highresistance value of the high resistance state.
 8. The method of writinginto a nonvolatile semiconductor memory device according to claim 4,wherein the variable resistor is a MIS transistor.
 9. The method ofwriting into a nonvolatile semiconductor memory device according toclaim 4, wherein the variable resistor includes a plurality of resistorparallelly connected, and the resistor connecting to the resistancememory element is selected to thereby control the resistance values ofthe variable resistor.
 10. A nonvolatile semiconductor memory devicecomprising: a resistance memory element which memorizes a highresistance state and a low resistance state and switches between thehigh resistance state and the low resistance state by an application ofa voltage; a variable resistor parallelly connected to the resistancememory element; and a resistance control circuit which, when the voltageis applied to resistance memory element to switch the resistance memoryelement between the high resistance state and the low resistance state,sets a resistance value of the variable resistor corresponding to aresistance state of the resistance memory element so that a writingcircuit for applying the voltage to the resistance memory element, and asynthetic resistor of the resistance memory element and the variableresistor make the impedance-matching.
 11. The nonvolatile semiconductormemory device according to claim 10, wherein the resistance controlcircuit sets the resistance value of the variable resistor so that asynthetic resistance value of the resistance memory element and thevariable resistor is not more than a low resistance value of the lowresistance state.
 12. The nonvolatile semiconductor memory deviceaccording to claim 10, wherein the variable resistor is a MIStransistor.
 13. The nonvolatile semiconductor memory device according toclaim 10, wherein the variable resistor includes a plurality ofresistors parallelly connected, and the resistor connecting to theresistance memory element is selected by the resistance control circuitto thereby set the resistance value of the variable resistor.
 14. Anonvolatile semiconductor memory device comprising: a plurality ofmemory cells arranged in a matrix, each of which includes a resistancememory element which memorizes a high resistance state and a lowresistance state and switches between the high resistance state and thelow resistance state by an application of a voltage, and a selecttransistor having one terminal serially connected to one terminal of theresistance memory element; a plurality of first signal lines parallellyextended in a first direction, each signal line being connected to gateelectrodes of the select transistors of the memory cells arranged in thefirst direction; a plurality of second signal lines parallelly extendedin a second direction intersecting the first direction, each signal linebeing connected to the other terminals of the resistance memory elementsof the memory cells arranged in the second direction; a plurality ofthird signal lines parallelly extended in the first direction or thesecond direction, each signal line being connected to the otherterminals of the select transistors of the memory cells arranged in thefirst direction or the second direction; a variable resistor parallellyconnected to the resistance memory element; and a resistance controlcircuit which, when the voltage is applied to resistance memory elementto switch the resistance memory element between the high resistancestate and the low resistance state, sets a resistance value of thevariable resistor corresponding to the resistance state of theresistance memory element so that a writing circuit for applying thevoltage to the resistance memory element, and a synthetic resistor ofthe resistance memory element and the variable resistor make theimpedance-matching.
 15. The nonvolatile semiconductor memory deviceaccording to claim 14, wherein the variable resistor is disposed betweenthe second signal line and the third signal line associated with thememory cells arranged in the second direction.
 16. The nonvolatilesemiconductor memory device according to claim 14, in which the variableresistor is respectively provided in each of the memory cells, and whichfurther comprises a plurality of fourth signal lines parallelly extendedin the first direction, each signal line being connected to gateelectrodes of the variable resistors of the memory cells arranged in thefirst direction.